In a CMOS circuit, current flows therethrough when the output value changes. In particular, if the CMOS circuit is operated at a fast speed, then the current is increased, and a large current will flow in a short period of time. This current causes noise to be generated at the power supply line and the ground line. In order to reduce the noise, a bypass capacitor may be connected between the power source and the ground to supply electric charges thereto.
In Japanese Patent Application Laid-Open No. 62-237756 ("MOS Integrated Circuit"), there is disclosed a method of forming the foregoing bypass capacitor on a semiconductor chip. This is intended for forming the bypass capacitor between a power supply line 1 and a substrate, that is, a chip 10 by forming an oxide film 3, which is similar to the gate oxide film, below the power supply line 1 lying on the chip 10, as shown in FIG. 1. However, in the conventional process of making the CMOS integrated circuit, since an electrically conductive film is formed on the gate oxide film by using polysilicon or polycide, which is high in resistivity, if only the oxide film similar to the gate oxide film is formed below the power supply line made of the polysilicon or polycide, parasitic resistance is increased and the effect of eliminating noise becomes low.
In Japanese Patent Application Laid-Open No. 2-144936 ("Semiconductor Integrated Circuit Device"), there is disclosed a method of forming a bypass capacitor in the wiring area of the gate array. This is intended for forming the gate oxide film 3 in the wiring area 11, on which the gate 4 is formed, as shown in FIG. 2. The area of the gate oxide film is made to extend up to the power supply line 1 to be connected through a contact 5 to the power source while the gate is made to extend up to the ground line 2 to be connected to the ground. A portion where the gate oxide film and the gate are overlapped forms a capacitor, which forms the bypass capacitor. However, since the wiring area of the gate array is wide, the parasitic resistance of the gate oxide film area and the gate is still increased, and the effect of eliminating the noise is low. Further, in an entirely laid-out gate array which provides no special wiring area, this method cannot be used.
In the proceedings of the 1990 IEEE International Solid-State Circuit Conference, page 48, left column, third paragraph and the slide supplement, page 36, there is described a method of suppressing the parasitic resistance sufficiently small by connecting the capacitor similar in construction to the MOS transistor, in which the size of the gate 4 is limited to 12.5 .mu.m in width (corresponding to the channel length) and 150 .mu.m in length, to the nMOS transistor in parallel, as shown in FIG. 3, and by applying power source potential to the gate and ground potential to the source/drain. This is intended for determining the configuration of the capacity area made of the gate 4 and the gate oxide film 3 so that the area and the time constant become optimal. However, in the case of this size, if they are accommodated below the power supply wiring, it is necessary to set the width of the power supply wiring to more than 150 .mu.m. Further, since the gate electrode is thin such as 12.5 .mu.m in width, there is a possibility that it cannot cope with more higher operating speed in the future when the sheet resistance of the gate layer is high.